HPL TECHNOLOGIES INC
Previous company name
HEURISTIC PHYSICS LABORATORIES INC
Name change date
The private limited liability company is engaged in the provision of yield optimization software for companies involved in the design, fabrication and testing of semiconductors and flat panel displays (fpds). In the year 2005, the company was completely acquired by Synopsis. Previously known as Heuristic Physics Laboratories Inc., its registered head office is located in San Jose, California.
The company enables manufacturers of semiconductors and fpds to identify and correct yielding factors in its design, technology development and manufacturing processes. It also provides an integrated suite of yield enhancement software solutions which allows chip companies to collect data from the design, fabrication, and test stages of production, then compile and analyze the information from a graphical user interface. Its software is also used in production of flat-panel displays. In addition, the company’s products include Odyssey, Memory yieldirector, Dssa sentry, Yieldprojector, cell designer, recipe management and editing (RME), and Odyssey-fpd.
HPL Technologies, Inc. (HPL) is engaged in the sale, support and providing of services related to the yield optimization software it designs for companies involved in the design, fabrication and testing of semiconductors and flat panel displays (FPDs). By combining its configurable enterprise software platforms and TestChip Intellectual Property (TestChip IP), the Company enables manufacturers of semiconductors and FPDs to identify and correct yield-limiting factors in their design, technology development and manufacturing processes. HPL’s products include Odyssey, Memory YIELDirector (MYD), DSSA Sentry, YieldProjector, Cell Designer, Recipe Management and Editing (RME), and Odyssey-FPD. It also offers TestChip products and services to semiconductor companies.The Company’s customers include integrated device manufacturers, fabless semiconductor companies and semiconductor equipment original equipment manufacturers.
Description and history
HPL Technologies, Inc. (HPL) is engaged in the sale, support and providing of services related to the yield optimization software it designs for companies involved in the design, fabrication and testing of semiconductors and flat panel displays (FPDs). By combining its configurable enterprise software platforms and TestChip Intellectual Property (TestChip IP), the Company enables manufacturers of semiconductors and FPDs to identify and correct yield-limiting factors in their design, technology development and manufacturing processes. HPL provides an integrated suite of yield enhancement software solutions that enables customers to optimize yields in all three stages of semiconductor development: process technology development, design and manufacturing. The Company’s products include Odyssey, Memory YIELDirector (MYD), DSSA Sentry, YieldProjector, Cell Designer, Recipe Management and Editing (RME), and Odyssey-FPD. HPL also offers TestChip products and services to semiconductor companies. The Company’s customers include integrated device manufacturers, fabless semiconductor companies and semiconductor equipment original equipment manufacturers.
Odyssey is the Company’s defect and yield data management solution. Odyssey and its predecessors are in use at over 70 manufacturing sites worldwide. It has an open and equipment vendor-neutral architecture that supports inspection, review and classification tools with a range of charting, wafer mapping, statistical analysis and lot dispositioning solutions. Odyssey simplifies and automates in-line defect analysis, reduces cycle times and enables engineers to address other critical yield-limiting issues. It also correlates different data types to deduce the root cause of manufacturing problems. Odyssey includes several optional analysis modules, including metrology, parametric, BIN, BIT and WIP.
MYD accelerates yield learning and problem resolution for dynamic random access memory (DRAM), static random access memory (SRAM) and flash memory arrays on semiconductor devices. It automates analysis of fab and test data for all memory types, including embedded memory. Using analysis algorithms, MYD automatically descrambles and classifies failing bitmaps into signatures, and correlates them with in-line defect inspection data to determine defect kill ratios. It also helps correlate bitmap failures with fatal defects (defects that cause failures in the device) to isolate the root causes of failure mechanisms in memories.
DSSA Sentry is a tool that employs defect spatial signature analysis (DSSA) algorithms to automatically classify the distributions of defects found on semiconductor wafers. These distributions appear visually as streaks, lines or other noticeable patterns of defects. By detecting these patterns or signatures early in the process, potential yield killers can be caught and the problem sources can be identified and fixed. Critical signatures like connection management protocol (CMP) and handling scratches, photo-lithography induced repeaters and streaks are detected by the DSSA sentry tool.
YieldProjector enables design engineers to improve the projected yield of a design before it reaches the manufacturing process. YieldProjector simulates the yield impact of a range of random defects on a design’s layout, based on statistical information from similar manufacturing process. It calculates the probable number of fatal defects on each layer of the design along with the projected yield of that layer. YieldProjector graphically highlights yield limiters in the design layout, so that the design engineers can compare various layout options and feature usage to improve a design’s immunity to random manufacturing defects.
Cell Designer addresses the core issue of design for manufacturability (DFM), that is predicting the electrical performance of a circuit manufactured on silicon in a specific process. Using tight integration between process and circuit simulation environments, Cell Designer enables what-if analysis and fast and interactive operation. Cell Designer can be applied to a variety of design styles, including memory, standard cell and custom logic. The Company markets and sells Cell Designer under an agreement with Sequoia Design Systems, Inc., the developer of the product.
Recipe Management and Editing
RME is a universal enterprise solution that facilitates the management and control of process recipes from a central repository. Process recipes are used to control the program process and metrology tools at every step in a semiconductor manufacturing process. RME reduces product scrap, improves yield and increases productivity of semiconductor fabs. An off-line editing module allows engineers to edit process recipes at their desk or anywhere on the corporate intranet without sacrificing security or increasing tool downtime.
Odyssey-FPD is a yield-optimization solution built specifically to address the challenges of FPD manufacturers. Odyssey-FPD leverages HPL’s Odyssey platform. This enables FPD customers to integrate relevant manufacturing data, including defect, parametric and test, into a seamless yield optimization environment.
TestChip Technologies Products and Services
The Company’s TestChip products address the needs of semiconductor companies in many aspects of process technology development, design and manufacturing. HPL’s TestChip products provide capabilities to accelerate semiconductor process technology development to the 65-nanometer node and beyond. In addition, for advanced technology nodes, these products provide methods for semiconductor manufacturing process characterization and monitoring. Semiconductor manufacturers have used TestChip solutions for more than eight years, at seven technology nodes and across multiple process technologies, such as complementary metal-oxide semiconductor (CMOS), bipolar complementary metal-oxide semiconductor (BiCMOS), radio frequency (RF) and analog. The Company has completed TestChip projects for technology nodes ranging from 350 nanometer to 45 nanometer.
The TestChip product line consists of a library of IP and TestChip circuits, supplemented by software products and services. HPL’s TestChip IP contains over 1,500 standard module elements to address the full breadth of advanced CMOS technology development concerns, including 193-nanometer lithography, copper and low-k interconnect integration and advanced transistor development. The TestChip IP also contains elements for improving yield in test structures, non-volatile memory, silicon-on-insulator (SOI), high-power devices, silicon germanium and RF devices.
HPL’s TestChip TechXpress array technology platforms alleviate many issues involved in sub-130 nanometer technology development and monitoring. The TechXpress Array Family comprises three technology platforms: TDSRAM, TDROM and TDParametric. From these technology platforms, the Company has generated over 20 different TestChip solutions that span the entire semiconductor lifecycle, each targeted at solving specific problems encountered at the various stages of process life cycle. The TDSRAM is used for bitcell development and process qualification. The TDSRAM bit is designed to measure key process parameters and is more sensitive to variations and yield issues than a conventional SRAM design. It can also be used to measure defect densities during volume manufacturing. The TDROM measures process excursion and design rule skews, making it suitable for process characterization and monitoring. The TDParametric array is capable of measuring the intrinsic electrical properties of the process. It produces a parametric response that provides a finer resolution of the measurement. TDParametric can be used, among other things, for via resistance measurements and field-effect transistor (FET) matching effects measurements.
TestChip Advantage is an analysis and data reduction software based on the Company’s yield management software. Using the TestChip Advantage templates and database, the Company captures the knowledge and intent of the various experiments during the design phase. Yield engineers can access the wafer results to analyze process issues and shifts prior to product yield loss. It allows the customer to view results grouped by experiment type, by layer and by figures of merit. Both bit map and parametric data are available with the ability to do statistical analysis of parameters over multiple wafers and lots. TestChip Advantage also enables the customer to do split lot analysis and to classify wafers based on different process equipment used.
The Company competes with Yield Dynamics and PDF Solutions.
Previously known as Heuristic Physics Laboratories Inc
Engaged in the provision of yield optimization software for companies involved in the design, fabrication and testing of semiconductors and flat panel displays (fpds)
US SIC Code
2033, Gateway Place
City province or state postal code
95110, SAN JOSE, CA
Phone: +1 408 437 1466
Fax: +1 408 437 1488
Country address: UNITED STATES OF AMERICA
Website url: www.hpl.com